1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile ferroelectric memory.
2. Related Art
Semiconductor memories are used for main memories of large-sized computers, personal computers, household electrical appliances, mobile phones or the like. Nonvolatile ferroelectric memories using ferroelectric capacitors can rewrite at 1012 or more times, have about the same reading/writing times as those of DRAMs, and can operate at a low voltage (1 V to 5 V, for example).
Ferroelectric memories described in Japanese Patent Application Laid-open Nos. H10-255483, H11-177036, and No. 2000-22010 can achieve a high-speed operation of plate lines by sharing the plate lines and plate-line driving circuits. However, on the other hand, a reading charge and a writing charge are transmitted from memory cells to bit lines or from bit lines to memory cells, via plural cell transistors connected in series. Therefore, addition of a delay component (parasitic capacitance) of the series cell transistors occurs in the bit lines, resulting in a limitation of the high-speed operation of the memories. When the number of series-connected memory cells is decreased, this delay component (parasitic capacitance) is decreased. However, chips cannot be downscaled.
Japanese Patent Application Laid-open No. 2005-209321 proposes a ferroelectric memory having a system that solves operation delay due to serial connection of memory cells. However, a unit cell of the ferroelectric memory described in Japanese Patent Application Laid-open No. 2005-209321 is larger than unit cells described in Japanese Patent Application Laid-open Nos. H10-255483, H11-177036, and No. 2000-22010. Therefore, the ferroelectric memory described in Japanese Patent Application Laid-open No. 2005-209321 operates faster than the ferroelectric memories described in Japanese Patent Application Laid-open Nos. H10-255483, H11-177036, and No. 2000-22010, but the unit cell is larger than those of the ferroelectric memories described in Japanese Patent Application Laid-open Nos. H10-255483, H11-177036, and No. 2000-22010.